With the rapid development on semiconductor technology, a carrier mobility enhanced technology has attracted extensive research and applications. The drive current of a MOS device may be increased by increasing the carrier mobility of its channel region, thus the performance of the CMOS device may be improved.
Because the band gap and carrier mobility of silicon material may be changed by a stress, improving the performance of CMOS devices by the stress has become a more and more common method. Specifically, by properly controlling the stress, the carrier mobility of the MOS devices may be increased, and the drive current may be increased, where the carriers of an NMOS transistor are electrons; and the carriers of a PMOS transistor are holes. Thus, the performance of MOS transistor may be significantly enhanced by increasing the carrier mobility.
The embedded SiGe technology is a common method to generate stress in the CMOS devices. The embedded SiGe technology may include forming a SiGe layer before forming a source region and a drain region; followed by doping the SiGe layer to form the source region and the drain region. A compressive stress may be generated because of the lattice mismatch between the silicon substrate and the embedded SiGe, thus the performance of the PMOS transistor may be improved.
Theoretically the embedded SiGe technology may increase the carrier mobility of transistors to a certain extent. However, in practical fabrication processes of the transistors, the quality of the embedded SiGe may need further improvements. The disclosed methods and devices are directed to solve one or more problems set forth above and other problems.